Chap. 1 - The Evolution of the Structure of MOSFETS 1
Chap. 2 - 300-MM Silicon Wafers 17
Chap. 3 - Gate Dielectrics: Thin-Gate Oxides 75
Chap. 4 - High-k Dielectrics 145
Chap. 5 - The Structure of Deep-Submicron MOSFETS: 181
Retrograde-Wells; Super-Steep Retrograde Channel Doping; Drain Engineering; Punchthrough-Control Implants
Chap. 6 - Deep-Submicron Lithography I: Photoresists 227
Chap. 7 - Deep-Submicron Lithography II: Optics & Hardware 259
Chap. 8 - Chemical-Mechanical Polishing (CMP) 313
Chap. 9 - Shallow-Trench Isolation (STI) 433
Chap. 10 - Silicon-Germanium (Si-Ge) Technology 475
Chap. 11 - Silicon-on-Insulator Technology (SOI) 501
Chap. 12 - Multilevel Interconnects for ULSI 573
Chap. 13 - Polycides & Salicides of TiSi2, CoSi2 & NiSi 603
Chap. 14 - Low-k Dielectrics 639
Chap. 15 - Dual-Damascene Interconnects 671
Chap. 16 - Copper Interconnect Process Technology 711
INDEX