Semiconductor Training
The Semiconductor Decision-Makers' Nightmare!
Are You Afraid of Making Wrong Technology Choices Because You
Don't Have the Information to Recognize "Bullet-Proof" Solutions?
Attending This Unique Seminar is the Fastest Way
for You to Obtain such State-of-the-Art Knowledge
"ADVANCED SILICON PROCESSING - 2007"
The Tra nsition from Microelectronics to Nanotechnology
May 21, 22, 23, 2007: Santa Clara, CA
In today's competitive work-environment
it's hard enough to just do your job.
Yet, new device-structures, processes &
materials continually emerge. Striving to keep up with these fast-breaking developments
is like "trying to drink from a firehose."
This is the only Seminar of 2007 that offers
a detailed survey of the State-of-the-Art of nanoscale-CMOS (65-nm & smaller) & the innovations proposed to build such ICs.
Get the benefit of Dr. Wolf's renowned insight
& analysis about key advances & challenges of the "Top-10 Breakthroughs of 2007."
"Dr. Wolf has a unique ability to read the literature & compile relevant information in an understandable format for others to digest ..." Dr. Richard Fair, MRS Bulletin November 2003
"Excellent Course" Z. Guo, Intel Corp.
"Dr. Wolf is very up-to-date on the full range of semicounductor manufacturing issues ... this class is a major help for anyone trying to learn about them." G. McCall, Tokyo Electron
"This seminar is the best complementary material to the ITRS Roadmap. It outlines many of the solutions being pursued to overcome the Red-Brick Wall." N. Shah, Aviza Technology
REGISTER NOW
This Annual Event is not expected to be held again until 2008
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1. INTRODUCTION & WHO SHOULD ATTEND
Conventional “top-down” microelectronics has entered the realm of nanotechnology. Dimensions of CMOS devices in 2007 are comparable to those of the novel structures
being explored in the new fields of “bottom-up” nano- and molecular electronics. The push for nanotechnology draws both on its’ future potential and its' adopted applications.
This Groundbreaking Seminar will address both approaches & discuss challenges facing the electronics industry in attempting to progress along both paths. It will also focus on
the intersection of top-down & bottom-up electronics, & what this may mean to future semiconductor technology.
If you are going to attend only a single seminar or training-class in 2007 ...
this should be the one!
What makes this the "must-attend" seminar for semiconductor industry professionals in 2007?
"A wonderful class. A wealth of information was provided ... fast paced."
"It focused on the new challenges and trends of the most advanced and future technologies." E. de Muizen, Sandisk
"Excellent breadth and depth of knowledge ... very thorough and pertinent."
Simply put, no other seminar matches this one in substance, scope, expertise, &
objectivity. Here's what separates "Advanced Silicon Processing - 2007" from the rest.
More valuable-information is packed into this premier seminar than any other
You get 3-Days of detailed coverage about the latest news on emerging technologies
for nanoscale-CMOS. These are the processes, materials, & devices that will define
the next generations of CMOS ICs, including 65-nm & 45-nm CMOS. Other than a
one-day course taught at the IEDM in December 2005 (which attracted over 300 attendees!), we know of no other seminar that offers this type of information in 2007.
"Good intro to the literature ... saves time in researching subjects ... Clear explanations ... It is obvious you've spent a great deal of time studying the material. Thank you!"
Our trademark expertise provides a clear perspective of the state-of-the-art
The descriptions & analysis we give of the latest candidates for each technology solution are unbiased and non-marketing-driven. Unlike the agendas of many recent "Nano Conferences," there is no spin, or hype about the next "killer-app" or "novel" device structure. Just solid, honest, up-to-date information (and plenty of references).
"Explained the reasons why the technology went the way it did, without a marketing spin."
The instructor, Dr. Stanley Wolf, has a proven educational track-record
Lattice Press has launched this educational event on the strong foundation of being the recognized leader in semiconductor training. We have offered popular courses on IC fabrication through UC Berkeley Extension for more than 20 years. Over 3000 microelectronic professionals from more than 75 companies & institutions have enrolled in these seminars. The May 2006 version of this Seminar was Sold Out!
Our Textbooks are Valuable Takeaways
Students use them as References long after the Class is over. For this seminar, a copy of "Silicon Processing for the VLSI - Vol. 4," is included in the seminar fee.
Networking Opportunities with Your Peers
WHO SHOULD ATTEND
The seminar is designed for semiconductor professionals who need to have a thorough
grasp of the state-of-the-art of silicon processing & device structures in 2007, & who
want to be "one step ahead."
It is a "Must-Attend" event for high-level decision-makers from across the semiconductor industry - including managers from chip manufacturers, equipment suppliers, design firms, OEMs, government, and more.
The material should also be of keen interest to scientists and engineers working in the following roles: Semiconductor Process Development; Process Integration; Device
Engineering; IC Product-Engineering and Marketing; Process-Equipment Design & Process Support; IC Fabrication Module-Managers who wish to broaden their technical foundations; VLSI Designers; Foundry Liason Engineers; Reliability, Quality, & Failure Analysis Engineers; Materials and Chemicals Suppliers to the Semiconductor Industry; Wafer-Fab Managers.
SEMINAR FEE
The fee is: $1795
This includes: a) Three full days of instruction (2.0 ceu); b) A copy of "Silicon Processing for the VLSI Era: Vol. 4 - Deep-Submicron Process Technology," by Dr. Stanley Wolf ©2002 (a $229.00 value); c) A comprehensive set of Course Notes (a $595.00 value); d) Three lunches & daily refreshments.
Attendance in this course will be limited. (The May 2006 Seminar was Sold Out!)
As an Annual Event, it is not expected to be conducted again until 2008.
REGISTER NOW to ensure your seat!
SCHEDULE
Monday-Wednesday, May 21, 22, 23 2007
Check-In: 8:00-8:30 AM, first day
Lectures:
8:30 - 4:30 Monday
8:30 - 4:30 Tuesday
8:30 - 4:30 Wednesday
Lunch breaks: noon-1:00 pm (Lunches are included as part of the Course Fee)
LOCATION
The seminar will be conducted on May 21, 22, 23 2007 at:
Hilton Santa Clara Hotel
4949 Great America Parkway
Santa Clara CA 95054
Ph: (408) 330-0001
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2. DETAILED CONTENTS OF THE SEMINAR-TOPICS
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1. S trained-Silicon For
Enhanced MOSFET Performance
The hottest topic in IC-processing in 2007 is arguably “Strained Silicon.” Straining the channel-region of silicon-MOSFETs can boost chip-speeds. That is, by stretching or squeezing the silicon crystal lattice, chips with 35% faster-speeds have been built.
In-process strain-inducing steps are the first ones that have been incoporated in manufacturing ICs. Other "extra" steps (such as growing strained-Si layers on Si-Ge templates) are being pursued as additional device-enhancement methods. Strained-Si CMOS was first introduced at the 90-nm generation, and 65-nm & 45-nm will use more of it.
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Introduction to the Physics of Strained-Silicon:
Solid-State-Physics Concepts of How Straining a Silicon Lattice
Impacts Carrier Transport: E vs. k Diagrams; Definition of me, mn,
& mp. Energy-Band Structure of Si & How it is Distorted by Strain,
Leading to Changes in Carrier Effective-Mass & Mobility; Application of
Strain To Enhance Carrier-Mobility (& Increase Performance of NFETs/PFETs).
Creation of Uniaxial Strain with Process-Induced Strain:
Tensile-Strain Enhancement of NMOS Performance; Problem of PMOS Performance-Degradation by Tensile Strain; Enhancing Hole-Mobility with Compressive Strain.Tensile & Compressive Stressor Films (PECVD Nitrides), Recessed Si-Ge Source/Drain Regions Deposited by Selective Epitaxy, "Stress Memorization."
Techniques for Creating Biaxial Strain in Silicon Wafers:
Epitaxially-Deposited Si-Layers on Relaxed Si-Ge Templates:Graded Buffer Si-Ge Sublayers; Defect-Related Issues in Epitaxially-Based Strained-Layers;
State-of-the-Art of Strained-Silicon Devices in 2007:
Strained Si on SOI-Wafers & High-k/Metal-Gate MOSFETs;
Strained-Si in 45-nm CMOS; Reliability Issues; Germanium-Layers as
Channels in Future MOSFETs – Pros & Cons.
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2. HIGH-k & ULTRA-THIN-SiON MOSFET GATE-DIELECTRICS:
Nanoscale-CMOS Gate-Stack-Engineering - Part 1
Im plementing high-k dielectrics into MOSFET gate-stacks
becomes more attractive as CMOS is scaled below 45-nm. Use of such high-k layers will be most important in low-power (portable) electronic systems, where leakage-current is a critical issue.
Yet, replacing SiO2 (or SiON) as the gate-dielectric is a major challenge, and successful implementation of this goal is requiring a sustained technological effort. This presentation describes the state-of-the-art of such thin gate-dielectric layers in 2007, as well as future trends.
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Scaling Gate-Oxide Thickness & Motivation for
Switching to High-k Dielectrics:
Why Must the Gate Dielectric be Scaled for Each CMOS Generation?;
Gate-Dielectric Materials; Properties of Ultra-Thin-SiO2 Layers;
Quantum-Mechanical Tunneling-Leakage Current vs. Oxide Thickness;
Effective-Oxide Thickness (EOT); Nitridation of Thin Oxides to Reduce
Boron-Penetration & Increase Film k-Value (& EOT).
Candidate Materials for High-k Dielectrics:
Silicon Nitride (Si3N4); Hafnium Oxide (HfO2); Nitrogen-Doped Hafnium
Silicate (HfSiON): High-k Gate Dielectrics: Now or Never?
High-k Dielectric Film-Deposition Techniques:
Chemical-Vapor Deposition (CVD); Atomic-Layer Deposition (ALD);
Metallo-Organic CVD (MOCVD); Physical Vapor Deposition (PVD);
Nitridation & Interface Preparation.
Process Integration Challenges of High-k Gate Dielectrics:
MOSFET Carrier-Mobility Degradation; Interface Charges; Fermi-Level Pinning
with Polysilicon Gate-Electrode; Penetration of High-k Layers by Dopants
from Polysilicon (or Metal-Atoms from Metal Gates); Crystallization of
Amorphous Dielectric Layer under High-T Processing; Hi-k Dielectric Reliability Questions.
Current Status and Future Prospects for High-k Materials
in Gate-Stack Applications
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3. METAL-GATES FOR ADVANCED MOSFETS:
Nanoscale-CMOS Gate-Stack-Engineering - Part 2
 Highly-doped polysilicon has been the gate-material in MOSFETs for more than 25 years. Dual-doped poly was incorporated into CMOS technologies about 10 years ago.
For 45-nm CMOS, however, polysilicon may have run out of gas (due to poly-depletion effects, Fermi-Level pinning in MOSFETS with high-k gate dielectrics; high-resistance of scaled poly films; & the reaction of polysilicon with metals in high-k gate-dielectric materials).
This presentation examines the physical effects that limit the future of polysilicon, & then discusses the advantages of using metal-gates as a replacement. The various candidate metal-gate materials are surveyed. The current problems that accompany their use are also identified, and the status of metal-gate technology today is summarized.
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Motivation for Use of Metal Gates:
High-Resistivity of Thin Polysilicon Gate Films; Boron Penetration
of Thin Gate-Dielectric Layers in PMOSFETs; Polysilicon-Depletion
Effects; Fermi-Level-Pinning in Polysilicon/High-k Gate stacks;
Reaction of Polysilicon with the Metal-Oxides of High-k Films;
Adopting Metal-Gates to Reduce of Gate-Leakage Current due to Tunneling
Candidate Metal-Gate Materials:
Mid-Band-Gap Metals (TiN, TaN); Fully-Silicided Gate Materials (NiSi FUSI);
Band-Edge-Metals (Dual-Metal Gates – for p & n-type MOSFETs); Tunable
Work-Function Metal Gates: Doping FUSI; Bi-Metal Layers (Ru-Ta Alloys).
Current Status & Unresolved Issues:
Mobility Issues; VT Instabilities; Reliability; Contamination of Si by Gate-Metal atoms.
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4. Ultra-Shallow Source/Drain Junctions: For 45-nm CMOS & Beyond
As transistor lateral-dimensions are reduced to improve speed-performance & functional density (chiefly by shrinking MOSFET gate lengths), the Source/Drain (S/D) junction depths must also become shallower.
For CMOS below 90-nm, these depths must be as small as ~30-nm. While low-energy ion implantation, spike-RTP-annealing, & salicides have been used in recent CMOS generations to form such S/Ds, these approaches are hitting the “red-brick wall.”
New techniques, such as selective epitaxially-deposited raised-source/drains, and doped Si-Ge recessed S/Ds are being actively pursued to confront this roadblock. This presentation examines the status of these technologies in 2006.
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S/D Junction Scaling Limits: Parasitic Series Resistances:
Spreading, Accumulation & Contact Resistances; Transient Enhanced Diffusion (TED);
Limitations of Conventional Junction-Formation Processes:
Ultra-Low Energy Implants; Spike-RTP-Annealing; Need for Hyper-
Abrupt Junctions; Punchthrough Stopper Structures: HALO; LATIPS.
Potential Solutions:
Plasma Immersion Ion-Implant (PIII); Gas Immersion Laser Doping (GILD);
Co-Implantation; Flash-Lamp Annealing; Laser Annealing; Selective
Epitaxially-Deposited Raised S/Ds; Recessed Si-Ge S/D Junctions:
Dopant Diffusion in Si-Ge; Allows Abrupt-Junction Formation.
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5. SILICON-ON-INSULATOR (SOI)
Going forward, ICs must offer higher-performance, but at
lower power-dissipation. However, these two cir cuit
characteristics must be traded-off in conventional
CMOS ICs.
Use of SOI may offer a way around this dilemma. That is why SOI is among the Top-10 Enabling Technologies of 2005. Our presentation describes the state-of-the-art of SOI in 2005, as well as trends for future advancements.
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Introduction to Silicon-on-Insulator (SOI):
What is SOI?; Advantages & Applications; History of SOI;
Extending the ITRS Roadmap with SOI.
Methods of Producing SOI Starting Wafers
Separation by Implanting Oxygen (SIMOX): High-Dose-SIMOX;
Low-Dose-SIMOX; Pros & Cons.
Wafer Bonding: Introduction; BESOI; Smart Cut®; Eltran®; Nanocleave.®
SOI MOSFET Device-Structures
Partially-Depleted (PD) MOSFETs:
Fully-Depleted (FD) Thin MOSFETs:
FD-SOI Solves Problems of Forming Ultra-Shallow S/D Junctions;
Process Technologies Used to Fabricate FD-SOI Devices.
Challenges Facing SOI:
Starting-Wafer Material-Quality; GOI; Floating-Body Effects &
Body-Contacts; Short-Channel Effects in SOI; High-Series Resistance
of Thin-S/D Regions: (Potential Solution: Complementary Salicide-Layers
on the Thin-Body S/D Regions); Self-Heating; Manufacturability of
Ultra-Thin-Body SOI MOSFETs; Reliability Issues.
Status of SOI in 2007
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6. COPPER/LOW-k INTERCONNECTS: Status & Trends - 2007
Scaling CMOS-technology into the nanotechnology regime allows hundreds of millions of devices to be put on a single chip. To make an IC from this many active-elements, on-chip interconnects must incorporate up to 10 wiring-levels. The parasitic RC-delay associated with IC interconnects is now the dominant factor limiting circuit-speed. To overcome this roadblock, Cu has replaced Al, and low-k materials are inserted between metal lines.
However, challenging problems a rise as CMOS is scaled
below 65-nm: Cu-resistivity significantly increases as the wire-width shrinks <0.2-µm; ultra-low-k films are so fragile that conventional CMP damages them; and new electromigration & stress failure-mechanisms arise in
narrow Cu-lines & vias. These issues are described in this presentation, together with the current status of Cu/low-k.
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Brief Introduction: Via-First Dual-Damascene Overview:
Copper - 2007:
Why Copper? Resistivity & Electromigration Benefits
Metal Barrier-Layers for Cu:
Materials: Ta; TaN; TaN/Ta Bilayers; Deposition Processes: I-PVD; ALD?
Cu Seed Layers: (& Direct-Plating on Ru Seed Layers)
Cu Electroplating:
Basic Process; Bottom-Up Filling Model ("CEAC" Model); Electroplating Tools
(New Tool-Configurations); Plating-Bath Control. Problems & Solutions:
Poor Via-Filling; Overfilling.
Post-Plating Cu Annealing:
Cu-Self-Annealing; Why Post-Plating Anneal-Step before CMP?
Problems: Increasing Resistance of Cu Resistivity with Shrinking
Line Sizes – Solutions.
CMP (Cu & Barrier Layer):
Current Processes; Problems: Dishing; Cu Corrosion; Ultra-Low-k
Dielectric Compatibility; Solutions: Low-Downforce, Abrasive-Free Polishing
(AFP); Electro-Chemical-Mechanical Polishing (ECMP).
Capping Diffusion-Barrier Layers:
SiN; SiCN; Selective Electroless Deposition of Metal-Capping Layer (CoWP).
Cu Process Integration & Reliability Issues:
Cu Stress-Voiding:
Models for Stress-Voiding Failure.
Electromigration Voiding:
Models for Electromigration Voiding Failure: Surface Transport;
Poor Adhesion of Cu to Capping Films; Contamination of Cu-Surface
Before Capping-Layer Deposition; Oxygen Diffusion thru Capping Layer
Solutions to These Obstacles.
Process Innovations to Overcome Reliability Problems:
Modified Barrier-Deposition Process; Bilayer Resist Process.
Low-k Dielectric Technology – 2007
Introduction to Low-k Materials:
Desired Characteristics of Low-k Dielectric Materials; General
Process Integration Issues Involving Low-k Films; Spin-On vs.
CVD Deposition Methods; Silicon vs. Carbon-Based Low-k Films.
1st-Generation Low-k Materials (k ~3.5):
CVD-Based: Fluorinated Silicate Glass (FSG); Spin-On (Inorganic:
Hydrogen & Methyl Silsesquioxanes HSQ & MSQ);
Organic: Aromatic Hydrocarbon Polymer: SiLK).
2nd-Generation Low-k Materials (k ~2.8):
CVD-Based: Carbon-Doped Siloxanes & Silicates:
Organo-Silicates (SiCOH); Spin-On PAE; Fluoro-polymer; BCB, HOSPs.
Ultra-Low-k Dielectrics (k <2.2):
Porous films & Porogens; Xerogels; Porous organic polymers.
Process Integration Challenges of Implementing Ultra-Low-k Dielectrics:
Need for Hard-Mask (to enable CMP); Pore-Sealing; Adhesion; Conversion
to Higher-k Material During Processing; Compatibility with CA-Resists.
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7. Advanced Lithography For Nano-CMOS: Immersion Lithography, Imprint Lithography, & Resolution-Enhancement Techniques
“Optical Lithography is Dead … Long Live Optical Lithography!”
The sc aling of IC dimensions is outpacing the introduction
of shorter-exposure wavelengths & higher–NA lenses. Thus, resolution enhancement techniques (RETs) are becoming indispensable for maintaining the aggressive scaling needed to sustain the financial & technical viability of the semiconductor industry.
This presentation covers such RETs as off-axis illumination (OAI), phase-shift-masks (PSM), optical proximity correction (OPC), and immersion lithography. Other novel approaches, such as bilayer-resist processes & imprint lithography will also be discussed.
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Lithography Trends in 2007:
Wavelength Reduction (248-nm, 193-nm, 157-nm; Larger NA;
k1-Reduction; DOF-Budget; Tool Cost & Throughput; Current
Approaches to Enable Optical Litho for Sub-65-nm CMOS Generations
Resolution Enhancement Technologies (RETs)
Optical Proximity Correction (OPC):
Iso-Dense Print-Bias; Serifs; Line-Jogs; Subresolution Scattering-Bars;
Mask-Error-Factor (MEEF); Penalties for Use (Mask Making Costs).
Phase-Shift Masking (PSM):
Priniciples; Alternating-PSM; Attenuating-PSM;
Strengths & Weaknesses of Each Type.
Off-Axis-Illumination (OAI):
Principles; Illumination Methods (Dipole; Quadrupole; Annular)
Immersion Lithography:
Principles; Increase Resolution & DOF; Immersion Exposure Tools &
Vendor Status; Immersion Resist Process; Ultra-High-NA Lens;
Doping to Increase Refractive-Index of Water; Challenges.
Imprint Lithography:
Principles, Materials (Imprint Polymers) & Tools (Imprint Presses);
Step-&-Flash Process; Status 2007.
Bilayer-Resist-Process:
for Via-First Dual-Damascene Applications.
EUV-Lithography: Status – 2007.
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8. EMERGING MEMORY-TECHNOLOGIES For the Nanoelectronics Era
The electronics industry would be revolutionized by memories that: 1) are as small & fast as a DRAM; 2) could to retain data without drawing power; & 3) could store information without having to maintain electric charge on a capacitor. Another important consideration is the sca lability of a new structure – How many generations can it survive?
There is a pressing need for a universal nonvolatile memory (UNM) that is fast, nonvolatile, and operates at low power. Such memory would be even more attractive if it was fully integratable with future logic and could continue today’s aggressive reduction in unit cost. This presentation describes in detail the emerging memory structures being developed in 2005 to achieve these goals, including the present state-of-the art of each technology.
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Introduction:
Need for a Universal Nonvolatile Memory (UNM): Drawbacks & Limits of
DRAM & FLASH Technologies; Limits Faced in Scaling DRAMs & FLASH Memory.
Ferroelectric RAMs (FRAMs):
History & Principle of Operation of FRAMs (including Ferroelectric
Materials); FRAM Cell-Architecture & Process Flow; FRAM Applications;
Pros & Cons of FRAMS; Current Status; Main Commercial Developers.
Magnetoresistive RAMs (MRAMS):
History & Principle of Operation of MRAMs (including Magnetoresistive
Materials, Magnetic Tunnel Junctions [MTJ]-Cells); MRAM Cell-
Architecture & Process Flow; FRAM Applications; Pros & Cons of
MRAMs; Current Status; Main Commercial Developers.
Phase-Change-RAMS (PC-RAMS)
aka Chalcogenide-RAMs or Ovonic-Unified Memories (OUM-RAMS):
History & Principle of Operation of PC-RAMs (including Chalcogenide
Materials); PC-RAM Cell-Architecture & Process Flow; PC-RAM Applications;
Pros & Cons of PC-RAMs; Current Status; Main Commercial Developers.
Programmable Metallization Cell memory (PMCm-RAMs)
MEMS-RAMs
Carbon-Nanotube-RAMs (CNT-RAMs)
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9. Beyond The Planar MOSFET: Devices for Nano-CMOS ICs (<45-nm)
The use of high-k dielectrics, metal gates, strained-Si & SOI will extend the life of the planar CMOS transistor to at least the end of the decade ... But then what?
Researchers are studying double-gate transistors to take
over when CMOS finally runs out of steam (e.g., FINFETs, MIGFETs). In double-gate devices (DGFETs) the gate is on both sides of the channel, giving much tighter control of the transistor’s ON & OFF states. Such DGFETs are likely to be first used in low-power applications, where control of OFF-state leakage current is critical. This presentation surveys the fabrication & characteristics of such novel FETs.
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IC Device & Chip-Architecture Trends in Sub-65-nm CMOS:
Performance; Density; Power-Dissipation; Conventional CMOS Device-
Scaling: What is the Limit?; Planar CMOS Structures for Low-Power &
High-Performance Applications.
Potential Device Architectures:
Double-Gate FETs; FINFETs; MIGFETs; MultiFINs
FINFET-DGCMOS Process Flow:
Gate-Width = 2xFin Height.
Advantages:
Allows Use of Undoped-Channels in FETs; Minimizes Short-Channel
Effects - Allows More Aggressive Device Scaling; Reduces Gate-Leakage Current.
Drawbacks/Issues:
More Complex Fabrication Process;
Choice of Gate-Electrode Material; Reliability.
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10. NANOELECTRONIC-COMPONENTS FROM THE BOTTOM-UP:
Carbon-Nanotubes - For MOSFETS & Nanoscale-CMOS Interconnects
As nanotechnology fabrication methods continue their rapid progress, the nanoelectronics era has arrived in the early 21st century. New nanostructures or nanodevices in the scale of 0.1-50 nm are under aggressive development.
This presentation focuses on the potential of carbon-nanotubes (CNTs) as the basis for a new nanoelectronics technology. CNTs are being groomed to augment - and perhaps ultimately replace - today’s ubiquitous silicon.
Applications to be described are CNT-FETs and CNT-interconnects. The properties, device structures, & synthesis techniques of CNTs being developed will be discussed.
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Introduction to Carbon-Nanotubes (CNT):
What is a CNT?; Physical Structure & Properties; Chirality Vector;
Single-Wall & Multi-Wall CNTs; Metallic & Semiconducting CNTs
History of CNTs:
Synthesizng CNTs: Metal-Catalyst Deposition & Catalytic CVD.
Carbon-Nanotubes as Active Transistors: Properties; Switching
Mechanism; Prototype Fabrication Techniques; MW-CNT-FETs;
CNT-Logic Gates. Challenges at 2006.
Carbon-Nanotubes as IC Interconnects
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| 3. PRINTER-FRIENDLY VERSION of the Course Brochure |
To Download a Printer-Friendly Version of the "Advanced Silicon Processing: 2007" Brochure, please Click on the Link below. This is a 3-MB file in the Adobe Acrobat pdf Format, and requires Adobe Acrobat Reader to View it.
CLICK HERE
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| 4. FREQUENTLY ASKED QUESTIONS (FAQs) ABOUT THIS SEMINAR:
What are the main benefits of attending this seminar?
The seminar is an authoritative source of information covering the details of the latest & most important processes, materials, & devices emerging in 2007. We guarantee that by attending you will come away with a sound grasp of the state-of-the-art of silicon processing in 2007. This knowledge can significantly benefit you in many ways, including:
- The hardcopy takeaways (Volume 4, and the fully-cited seminar notes), will be valuable references long-after the seminar is over.
- You'll be equipped to make better-informed decisions when facing technology challenges associated with new processes and materials.
- It will help prepare you for changes in job-assignment - and promotions!
- It will enhance your ability to communicate with colleagues, especially those outside of your own area of expertise (e.g., foundry liason tasks).
- You'll gain insights to identify possible causes of yield-crashes that arise when new materials or processes are implemented.
- Your broader knowledge-base will be useful when carrying-out design-of-experiment tasks.
- You will be able read the relevant literature more quickly (saving time) ... and with greater understanding.
- You'll have an opportunity to network with others who are also wrestling with the challenges encountered at the leading edges of technology. These interactions may allow you to share insights with fellow professionals about how to address such problems.
How can you be assured this seminar will be up to the state-of-the-art?
The course creator and instructor, Dr. Stanley Wolf, spends full-time studying the latest developments in the semiconductor industry. In the past 20 years he has converted this research into the most authoritative books on silicon processing & MOSFET device physices.
His ability to organize such information and present it logically & clearly has been lauded
by his peers. For example, Dr. Richard Fair, Endowed Professor at Duke University &
former Editor of the IEEE Proceedings, wrote in the November 2003 MRS Bulletin:
"Stanley Wolf has a unique ability to read the literature & compile relevant
information in an understandable format for others to digest ..."
Dr. Wolf strives to provide the latest details about the breakthroughs that are being reported in the open literature. For example, his presentations will include a careful
analysis of the papers presented at the most recent IEDM Meeting (Dec. 2006).
What about other seminars being offered on semiconductor technology in 2007?
It depends on what kind of information you need. Almost all other seminars being offered today are lower-level, introductory surveys that only cover the general topics of IC fabrication. (Many, in fact, describe silicon processing as it was practiced 10 years ago!) For workers just entering the industry, such basic overviews may be useful. But it is certainly not the kind of information being sought by seasoned semiconductor professionals.
What happened to Dr. Wolf’s previous Silicon Processing courses?
Like other pre-2000 training-classes, his Silicon Processing Courses were adversely impacted by the economic-downturn that followed the 2001 Tech-Crash and the events of 9/11.
Since then, Dr. Wolf has been developing this seminar in anticipation of an upturn in the economic climate. He envisioned that what the semiconductor industry would need is not a presentation containing introductory material, but instead a resource that would offer insights about what was currently happening (and what would likely be emerging in the near-term future).
Disappointed in the information you have been getting at the so-called “Nanotechnology Conferences”?
A new trend that has sprung up to replace hard-core technical seminars is the "Financial/Technical Conference." At least a dozen "Nanotechnology Conferences" have been held in the past year - & more are scheduled in the months ahead! But, these often turn out to be platforms for marketing presentations of new “gee-whiz” products, together with future "blue-sky" growth-predictions.
However, the highest profits of the semiconductor industry are based on products that exploit the leading-edge of reality. That's what our seminar promises to deliver information about, and not a collection of overblown predictions.
But, the problem facing working-engineers is that most don’t even have the time to keep up with the real leading-edge. They can't read all the journals, attend the conferences, and study the data published by the researchers developing these products - thus, the leading-edge keeps moving away from them.
An efficient way to catch-up is to come to this seminar!
Dr. Wolf works hard to keep a pulse on the latest developments. He continuously keeps an eye out for the most significant breakthroughs, and then distills these nuggets into a form easily digested by those who don’t have the time and energy to sift the raw data.
If you found the information in Dr. Wolf’s books valuable, this upcoming seminar is the way to get access to his latest insights about the cutting-edge technologies of 2007.
Why is Lattice Press sponsoring this seminar in 2007?
In the past, Dr. Wolf turned his ability to explain difficult concepts in a clear and logical format into printed-compendiums (i.e., books). His 4-Volume Series "Silicon Processing
for the VLSI Era," is considered by many to be the "Physicians Desk Reference" for the semiconductor process-engineering community.
Unfortunately, times have changed, & specialized texts of this type have become "sitting ducks." Because they are so easy to duplicate (without having to buy them), it is no longer economically feasible to write & publish highly-specialized reference books. (We sense that such forms of compiled knowledge are rapidly becoming a thing of the past!) In addition, while advances in technology makes information in such books quickly outdated, frequently revising books is economically impractical.
As a result, Dr. Wolf will now make his technical surveys available only to those who attend his seminars (or who become his private clients through subscription-based information products). It will also be easier and faster for him to update the information he offers (rather than having to update an entire book). Such material can also always contain the latest breakthroughs and trends. Likewise, irrelevant (or now-less-important material) can be deleted, saving readers from wasting time by assimilating obsolete data.
Why you will still be able to rely on Lattice Press to be your "Beacon to Information" about the latest breakthroughs of IC processing?
What makes our analysis especially valuable is that we are not the mouthpiece of any company or promotional firm, and we are not beholden to advertisers. Our only interest
is to provide customers with information about the latest & most significant technologies
by gleaning such insights from the open literature. These tutorials are made even more unique by the skills we have gained from following and writing about IC technology for nearly 30-years. For example, we believe that the background-science on which these new breakthroughs rely should first be reviewed. By understanding the “why” of a new approach, one can better judge whether it has a reasonable chance of succeeding (especially when compared to competing methods, perhaps based on other conceptual premises).
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5. INSTRUCTOR'S BIOGRAPHY
Stanley Wolf, Ph.D. is the creator and instructor of this seminar.
He is an internationally-r ecognized expert in the field of micro-
electronic education, having been involved with the semiconductor industry for over 30 years. Dr. Wolf is also the author of the best-selling four-volume series Silicon Processing for the VLSI Era, and a new full-color book on IC fabrication, titled Microchip Manufacturing (© 2004, Lattice Press). As a renowned lecturer on this subject, his audiences remember him for his technical depth, his broad industry experience, and his engaging speaking style.
Dr. Wolf received his Ph.D. from UC Santa Barbara, and then was a Member of the Technical Staff at the Hughes Aircraft Research Labs. Later, he served as a Professor of Electrical Engineering at CSULB. He was also an Instructor for the UC-Berkeley Engineering Extension for 20 years. He has authored 7 technical books, over 20 articles, and holds several patents. He has been a member of the IEEE and the Electrochemical Society for more than 25 years.
If you have any other questions about this seminar, you may e-mail Dr. Wolf directly at the latticepress website (see contact info at the bottom of this page) or call: 714-840-5010 - 9:00 A.M. - 5:00 P.M, PST. If you cannot attend the course but would like to obtain copies of the course text, it can be ordered directly from the Lattice Press website (www.latticepress.com). More information about other books written by Dr. Wolf (i.e.,
the 4-volume series Silicon Processing for the VLSI Era) can also be found there.
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| 6. REGISTRATION INFORMATION |
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| REGISTRATION FEE & SEMINAR LOCATION
Seminar Fee is: $1795
Group discounts are availble (call 714 840-5010 for more information)
The seminar will be conducted on May 21, 22, 23, 2007 at the:
Hilton Santa Clara Hotel
4949 Great America Parkway
Santa Clara CA 95054.
Phone: (408) 330-0001
HOW TO REGISTER
By Mail - Download & Print a copy of the pdf file of the Brochure (see Section 3).
Fill out and return the Registration Form provided on this Brochure. Mail to:
LATTICE PRESS
PO Box 340
Sunset Beach CA 90742
By Phone - You may register by phone if using Credit Card for payment (Ph:714-840-5010)
By FAX - You can FAX us a completed Registration Form (found in the pdf file of the
Brochure - see Section 3 & download & print this file). Send it via FAX to 562-592-1976.
Online - You can register online by filling out the Registration Form that appears when
you Click on the "Register Here" Button.
By Purchase Order - Companies, agencies, other organizations may pay by purchase order
PAYMENT
Registrations must be accompanied by the full payment or by purchase order authorization. You can pay by Check or Credit Card. Make checks payable to "LATTICE PRESS."
REGISTER ONLINE
You can REGISTER NOW by Clicking on the Register Button below, and filling out the Registration Form that appears. Your will receive written confirmation of Registration.
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CANCELLATION POLICY
Cancellations are subject to a 25% service charge. The seminar fee (less a 25% service charge) will be refunded if the cancellation is made at least one week prior to the first day of the seminar. Substitutes may be made at any time without penalty. Registrants who do not attend and do not cancel by written notification 7 days prior to the seminar date are liable for the full registration fee. No shows will be charged for the full reistration fee.
Lattice Press Cancellation Liability
In the event of cancellation of the seminar for any reason, Latice Press' liability is limited to the return of the full registration fee. We do not refund travel or other costs.
All Presentations
Will be produced by Dr. Stanley Wolf of Lattice Press. Some of them will also be given by him, but other experts will lecture on some of the subjects. Although Lattice Press makes every effort to ensure the high quality of its seminars, it may be necessary to make unforeseen changes in the agenda after the date of publication.
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© 2004 by LATTICE PRESS Sunset Beach CA - All Rights Reserved.
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