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PROLOGUE - Silicon Processing for the VLSI Era: Vol. 1 (2nd Edition)
by S. Wolf & R.N. Tauber
(Note: The material has been reformatted for faster page loading. Since the invention of the first integrated circuit in 1960, there has been an ever-increasing density of devices manufacturable on semiconductor substrates. Silicon technology has remained the dominant force in integrated circuit fabrication and is likely to retain this position in the foreseeable future. The number of devices manufactured on a single chip exceeded the generally accepted definition of very large scale integration, or VLSI (i.e., more than 100,000 devices per chip) in the mid-1970's (Fig. 1a). By 1986 this number had grown to over 1 million devices per chip (ULSI), and by 2000 had exceeded 1 billion devices per chip (e.g., the 1 GB DRAM). This increasing device count has been accompanied by a shrinking minimum feature size (Fig. 1b), which is expected to be smaller than 0.1 µm by 2004. Progress in ULSI manufacturing technology seems likely to continue to proceed in this manner. Further reductions in the unit cost per function, and in the power-delay product of ULSI devices, are projected. The entire saga of IC fabrication represents a remarkable application of scientific knowledge to the requirements of technology. This book represents an enthusiastic report on the state-of-the-art of ULSI silicon processing, as practiced at the time of its publication. |
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| Fig. 1 (a) Increase in the number of transistors per microprocessor chip versus year of introduction, for a variety of microprocessor designs. (© IEEE 1998) (b) Predictions of the decrease in minimum device feature size, junction depth, and gate oxide thickness versus time on integrated circuits, according to the SIA International Technology Roadmap for Semiconductors. |
| Figure 2 illustrates the sequence of steps that occurs in the course of manufacturing an integrated circuit. These steps can be grouped into two phases: 1) the design phase; and 2) the fabrication phase (Fig. 3). While this book is concerned only with the fabrication phase of this undertaking, it is also useful to briefly outline the steps of the design phase here. This provides the context which allows readers to perceive the role of silicon processing within the totality of integrated circuit manufacturing. Readers wishing to explore steps of the design phase in detail are referred to other technical literature, including the texts listed in References. 1, 2 and 3.
The desired functions and necessary operating specifications of the circuit are initially decided upon in the design phase. The chip is designed from the "top down." That is, the required large functional blocks are first identified. Next, their sub-blocks are defined, and finally the logic gates needed to implement the sub-blocks are chosen. Each logic gate is designed by appropriately connecting devices that are ultimately slated for fabrication on the Si wafers. Upon completion of these various levels of design, each level is rechecked to insure that correct functionality has been achieved. When all aspects of the circuit design are correct to the designer’s satisfaction, test vectors (that will be used to test the manufactured circuits), are generated from the schematic of the logic gates. The circuit is then layed out. The layout consists of sets of patterns that will be transferred to the silicon wafer. These patterns correspond to device regions or interconnect structures, and such patterns are sequentially transferred to the wafers as part of the wafer fabrication sequence (That is, through the use of photolithographic processes and a set of masks, see Fig. 4a). |
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| Fig. 2 Steps required for the manufacture of integrated circuits. |
| The result of each pattern-transfer step is a set of features created on the wafer surface. These features are generally either in the form of: a) an etched opening in a film (or region of the substrate), or b) a patterned feature of a film present on the surface (e.g., an interconnect line or pad). After the openings (or windows) are created by the pattern transfer step, either controlled quantities of dopant are added to the silicon substrate through the openings, another layer is deposited that makes contact to the underlying layer through the opening. In either case, device regions and structures that interconnect device regions, are produced by the patterning proces-ses and associated fabrication steps. A cross-section of a completed device is shown in Fig. 4b. |
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| Fig. 3 The wafer fabrication process sequence of integrated circuits. |
| While the circuit is designed from the “top down,” creation of the layout proceeds from the "bottom up." A variety of typical devices (e.g., transistors and resistors) are first layed out. Then, a set of cells representing the required primitive logic gates are created by interconnecting appropriate devices. Next, sub-blocks are generated by connecting these logic gates, and finally the functional blocks are layed out by connecting the sub-blocks. Additional items required by the circuit design are also incorporated during the layout process (e.g., power busses, clock-lines, and input-output pads).
The completed layout is then subjected to a set of design rule checks and propagation delay simulations to verify that correct implementation of the circuit has been achieved in layout form. Upon completion of this checking procedure, the layout information is ready to be used to generate a set of masks that will serve as tools for specifying circuit patterns on silicon wafers. The layout information is stored on a computer. |
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Fig. 4 (a) Example of the patterns transferred to a wafer during a seven-mask process sequence, and (b) Cross section of completed devices in a basic CMOS process.
In the three volumes of Silicon Processing for the VLSI Era integrated circuit manufacturing steps are described (Fig. 3). These steps start at the point where the layout information has been finalized. At that point procedures are utilized to convert the layout information stored on the computer, into a set of masks or reticles (as described in Chap. 13). The individual fabrication process modules associated with creating patterns, introducing dopants, and depositing films on silicon substrates (to form integrated circuit features) are also subjects of this volume. In Volume 2, information about how such individual process modules are combined to create complete ICs are covered in detail (namely the tasks of Process Integration). A brief discussion of process integration issues is also provided in Chaps. 15 and 16 of Volume 1. Volume 3 concentrates on the device physics of the submicron MOSFET and how device characteristics and the device processing steps are interrelated. In Vol. 1, background information on science and technology common to many IC fabrication steps is also provided (e.g., vacuum technology [Chap. 3], material properties of thin films [Chap. 5], and optical science for microlithography [Chap. 13]). A short description of the so-called back end of IC processing (i.e., assembly and packaging) is given in Chap. 17. These three books can be read selectively to glean specific information. References are made to other chapters of the texts to clarify points for readers who wish to use the text in this manner. REFERENCES |
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