Excerpt from: SILICON PROCESSING FOR THE VLSI ERA - Vol. 2
1.1 INTRODUCTION TO PROCESS INTEGRATION, pp 5-9
by Stanley Wolf, Ph.D.

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The text and graphics remain the same as pp. 5-9 in the book.
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The approach used in building integrated circuits on monolithic pieces of silicon involves the fabrication of successive layers of insulating, conducting, and semiconducting materials. Each layer is patterned to form a structure that performs a specific function, usually linked with surrounding areas and subsequent layers. The fabrication steps used to manufacture an integrated circuit must therefore be executed in a specific sequence, which constitutes an IC process flow (or process).

1.1.1 Process Sequence Used to Fabricate an Integrated-Circuit MOS Capacitor Structure.

A simple example of the sequence of steps that must be used to form an integrated circuit MOS capacitor is shown in Fig. 1-5. First, a relatively thick SiO2 layer is grown on a bare n-type Si substrate (using oxide-growth techniques, as described in Vol. 1, chap. 7). This oxide layer (Fig. 1-5a) serves to isolate the metallization-interconnect film deposited at the end of the process from the Si substrate.

Fig. 1-5 Process sequence for fabrication an MOS capacitor.
An opening in the SiO2 layer is then formed using a photolithographic process (Vol. 1, chaps. 12 & 13) and an etch process (see Vol. 1, chaps. 15 & 16). Boron atoms are ion-implanted into the wafer surface (Fig. 1-5b). Wherever an opening exists in the SiO2 layer, the boron atoms are implanted into the Si substrate. A sufficient implant dose is used to cause these regions to become p-type.

The energy of the implant and the SiO2 thickness are also selected so that the boron atoms do not penetrate to the Si wherever the SiO2 layer remains. In this manner, p-regions (which will serve as the lower plate of the MOS capacitor) are selectively formed in the Si. In addition, if the voltage between the p and n regions of the Si substrate keeps the pn junctions reverse-biased, the lower plates of any capacitors built on the same Si substrate will be junction-isolated from one another (see chap. 2).

The remaining steps are shown in Figs. 1-5c and 1-5d. A thin SiO2 film is grown over the exposed p-type Si region, and a contact hole is etched in the film to allow an Al film to make contact to the lower plate of the capacitor. The Al film, deposited next, also serves as the top plate of the capacitor. The formation of the contact holes and Al patterns involves alignment, another important process that must be successfully accomplished when integrating a process sequence.

The capacitor structure will function properly only if the two plates of the capacitor are isolated from each other, except where an intentional contact must be made. Therefore, if the Al pattern that serves as the top plate of the capacitor is misaligned (resulting in an accidental contact between the Al and the p-type Si region), the two plates of the capacitor will be shorted. This alignment restriction is one of the limitations faced in device miniaturization, as discussed in Volume 1, chapter 13.

1.1.2 Specifying a Process Sequence.

Once a process has been completely developed, a set of instructions is produced for fabrication of the specific technology. These instructions include the appropriate times, temperatures, gas flows, power settings, etc. needed for each process step in order for the desired structures to be produced.

The instructions also list the specifications of the device structures that should be achieved at the conclusion of each of the process steps (e.g., line width, sheet resistance, film thickness, and step height), as well as the inspections and measurements that must be made to ensure that these specifications have been met. This set of instructions accompanies the group of wafers (or lot) as it moves through the process, and is therefore known as a lot traveler, or run sheet.

Since integrated circuits are normally processed in batches (or lots), each of the steps is usually performed on all of the wafers in a lot before that lot is moved to the next processing step. As each step is completed, the fabrication worker (operator) responsible for that step indicates that the process step has been accomplished and records on the lot traveler the time of completion, as well as any required data concerning the process conditions, resultant measured parametric data, and any pertinent comments.

When a lot has been completed, the data gathered about all of the fabrication details of that process run is thus contained on the lot traveller. Lot travellers initially consisted of printed sheets of paper, but now they are stored on computers. Data concerning manufacturing details of each lot-fabrication sequence is entered directly into the computer.

1.1.3 Levels of Process Integration Tasks

From a general perspective, process integration involves the combining of various individual processes (described in Vol. 1) to produce IC structures (or even an entire IC). Process integration tasks can thus involve varying degrees of complexity. Examples of the levels at which such tasks can be performed can be grouped according to increasing complexity, as follows:

1. Development of a process sequence to modify an existing structure that is only one part of an integrated circuit. Two examples of such process-integration tasks are: (a) the development of a modified local-oxidation isolation structure with reduced bird's beak or boron channel-stop encroachment (see chap. 2), and (b) the improvement of the characteristics of a barrier-layer material used in metal-Si contacts (e.g., by replacing Ti with Ti:W; see chap. 3).

2. Development of a process sequence to produce a new device structure. Three examples of this are: (1) development of a selective epitaxial isolation structure to replace LOCOS (see chap. 2); (2) implementation of a double-level-metal (DLM) structure to replace a single-level-metal interconnect approach (see chap. 4); and (3) creation of a TiN local-interconnect structure for CMOS (chap. 3)

3. Enhancement of a complete process sequence by shrinking the minimum feature size used in the technology. While such "technology-shrinks" are generally less complex than the tasks involved in the development of an entirely-new complete-process sequence, they usually entail more than just the implementation of higher-resolution lithography processes. That is, many of the other processes must also be modified, and entirely new ones may need to be developed. Two examples of such technology evolution that have been detailed in the literature are 1) the shrinking of Intel's NMOS process from
NMOS I (L = 6 µm) to HMOS III (L = 1.5 µm), and 2) the shrinking of of AT&T's Twin-Tub CMOS process from CMOS I (L = 2 µm) to CMOS VI (L = 0.5 µm)

4. Implementation of a new technology through modification or enhancement of an older technology. Two examples of this type of process-integration effort are:

a. Development of an n-well CMOS process based on the experience gained from prior NMOS technology development. In this case, NMOS devices are fabricated in the p-substrate, using the same process sequence as in an NMOS process developed earlier, while the fabrication of PMOS devices in the n-well (and the integration of these process steps into the NMOS sequence) represent new process integration tasks.

b. Development of a BiCMOS process through integration of the steps needed to fabricate bipolar npn transistors into an existing CMOS process sequence (see Chap. 7)

5. Development of a new technology from scratch. Examples of this effort are the development of new CMOS and BiCMOS processes without reliance on the enhancement of older process sequences. This kind of effort is normally the most difficult, and so it is rarely attempted. When a new process is to be developed from scratch (especially where new materials are to be used), the effort required to establish the interrelationships among the various process steps can be extremely expensive and time consuming. A more conservative approach is to modify or enhance a previously developed process. Consequently, when a company decides to launch a line of products based on a new process sequence, it often purchases the technology details from a company that has already developed such a process. The acquired process technology can either be used as is, or enhanced

1.2 PROCESS-DEVELOPMENT AND PROCESS-INTEGRATION ISSUES

When a new process or device structure is proposed for development, the intent is to improve the circuit performance in some way or to build new products that could not be fabricated with existing technology. It is very important that the circuit designers, product engineers, device designers, and process engineers interact closely in such a development effort. The circuit designers and product engineers identify the performance requirements and package sizes needed for the applications to be served (e.g., SRAMs, ASICs, microprocessors, or logic circuits).

From these specifications, the device designers can target candidate device structures, as well as the various structural options and process flows that can be potentially investigated for achieving these goals. The process engineers can then work on finding new materials and innovative processes to implement the advanced device structures. The odds of developing new device structures that offer improved performance (while still meeting reliability and manufacturability constraints) are greatly enhanced when each of the members of a technology devel-opment team understands the goals and limitations of the other disciplines involved.

Several key issues must be considered when a process-integration task is to be undertaken. One of the most important is that virtually all of the steps in a process sequence are significantly interrelated. For example, each of the thermal cycles in a process sequence contributes to the total vertical and lateral diffusion effects in a process.

To end up with device structures that have the desired doping profiles at the end of a process sequence, it is necessary to take into account all of the thermal processing steps that a device undergoes. Furthermore, each new thermal step may impact the formation of defects in the silicon or may play a role in the chemical or morphological characteristics of the structures created in the IC. Since the fabrication steps are so strongly interrelated, once a process has been well established, a cardinal rule - which must be rigidly followed - is that no step in the process may be arbitrarily changed.

Nevertheless, when a new process is developed, it is obvious that at least some changes must be made to an existing process. The ability to predict the effect of a process change on the circuit or device electrical parameters is an important part of the process-integration effort. In the early days of integrated-circuit manufacturing, hand calculations of the doping profiles in the silicon and SiO2 based on simple one-dimensional analytical models were used to estimate the electrical characteristics of device structures fabricated using a particular process sequence.

These predicted estimates were then compared to the electrical characteristics measured following the completion of process runs which were designed according to the analytically determined process steps (trial-and error approach).

As device sizes grew smaller, however, such an approach proved to be inadequate. That is, two-dimensional effects within the device structures made the measured electrical characteristics deviate significantly from the characteristics predicted with one-dimensional models. To produce small-geometry devices with the desired electrical characteristics, device and process engineers had two options: (1) to perform more experiments, or (2) to use computer-aided simulation of the fabrication process to model the device structures that are obtained from a specific process sequence (Fig. 1-6).

The first option would mean a drastic increase in the costs and cycle time of new process integration. Furthermore, even if the experiments did yield adequately performing devices, if complicated processes and structures were involved, the result would still be poor physical insight and inadequate quantitative analysis of the factors governing device operation.
Fig. 1-6 Simulation and experiment are approaches to IC process development. Path A depicts the experimental approach. Path B is the approach that exploits computer-aided simulation. (Copyright IEEE, 1984).
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