SILICON PROCESSING FOR THE VLSI ERA now represents a series of texts designed to provide a comprehensive and up-to-date treatment of this important and rapidly-changing field. The volume in hand is the third of this series. Volume 1 - 2nd Edition (Process Technology) was published in 2000 and Volume 2- 1st Edition (Process Integration) in 1990. Volume 1 covers (in depth), the individual processes used in the fabrication of silicon VLSI circuits, such as: epitaxial growth, chemical vapor and physical vapor deposition of amorphous and polycrystalline films, thermal oxidation of silicon, diffusion, ion implantation, microlithography, and etching processes. Volume 2 describes how the individual processes described in Volume 1 are combined in various ways to produce silicon integrated circuits. This task is referred to as process integration.

Here, we treat the topics of submicron MOSFET device physics and the relationship between such device physics and submicron MOSFET fabrication. That is, an understanding of device physics has become even more important now that MOSFETs have crossed the long-channel frontier into the submicron realm. Device aspects that could once be ignored (because they cause only second-order effects in large MOS devices) are now significant.

Many device effects observed in submicron MOSFETs are impacted by the process technology used to fabricate them. Some of such effects include: short-channel effects on VT; RSCE (reverse-short-channel effects) DIBL (drain-induced barrier lowering); narrow-width effect; reverse-narrow-width effect; subsurface punchthrough in NMOSFETs; punchthrough in PMOSFETs; impact of the VT-adjust implant on subthreshold-swing, St; boron penetration of gate oxides in p+-poly-gate PMOSFETs, GIDL (gate-induced drain-leakage).

Others include the impact of process technology on the reliability and wearout of thin-gate oxides, including damage from plasma processing; hot-carrier degradation and drain-engineered MOSFET structures developed to combat the problem (including LDDs, LATID, “halo” implants, and asymmetrical MOSFETs); well-engineering by high-energy implants (including retrograde-well CMOS); ROXNOX (re-oxidized-nitrided oxides); and very-lightly-nitrided gate-oxides.

These and many other phenomena associated with submicron MOS fabrication can only be understood in the context of short-channel based MOSFET physics. Only with such an understanding can the relationship between circuit behavior, device design, and process technology of submicron MOSFETs be grasped.

Consequently, by gaining such an understanding, process engineers (and other microelectronic professionals) will better be able to contrbute to the task of successfully designing and manufacturing submicron ICs. One of our main purposes is thus to provide a text that treats both the topics of submicron MOSFET device physics and the phenomena associated with fabricating such devices.

Chapter 1 introduces the Process and Device Models employed in the early days the semiconductor industry. Such models were based on empirical data and/or simplified physical equations (e.g., the differential-equations in their one-dimensional form). In the submicron era, however, the more general forms of these differential-equations must be used to obtain accurate predictive capability of both the fabrication processes and the device physics.

Since this generally means that partial differential-equations in two- or three-dimensional form must be Solved, this can only be carried out by Numerical Analysis, performed with the aid of high-speed digital computers. Thus, Chapter 2 outlines the methodology of this approach.

To facilitate the discussion of submicron MOSFET device physics, we divide the topic into three chapters: The first of these, Chapter 3, deals with Basic MOS Theory and the MOS Capacitor.

The next, Chapter 4, covers Long-Channel MOSFETs and the circuit models developed to predict the drain-current characteristics of such devices.

Finally, Chapter 5 describes the Characteristics of the Short-Channel (i.e., the Submicron) MOSFET. This is the longest chapter of the book, and it includes the following topics: DIBL, subsurface punchthrough, the drain-current in saturation, simplified short-channel MOSFET circuit models, MOSFET scaling, and submicron MOSFETs.

Chapter 6 is concerned with Isolation Issues in Integrated Circuits, with an emphasis on CMOS technology.

Chapter 7 covers Thin Gate-Oxides, primarily with respect to Reliability & Growth.

Chapter 8 deals with Well-Formation in CMOS.

Chapter 9 focuses on Hot-Carrier Effects in MOSFETs, as well as on device-structures and processing-techniques that mitigate the detrimental aspect of such phenomena on MOSFETs. Problems are included at the end of each chapter to assist readers in gauging how well they have assimilated the material in the text.

A book of this length and diversity would not have been possible without the indirect and direct assistance of many other workers. To begin, virtually all of the information presented in this text is based on the research efforts of a countless number of scientists and engineers. Their contributions are recognized to a small degree by citing some of their articles in the references given at the end of each chapter.

The direct help came in a variety of forms, and was generously provided by many people. The text is a much better work as a result of this aid, and the authors express heartfelt thanks to those who gave of their time, energy, and intellect. Roy Montebin of Visionary Art Resources designed the cover, as well as those of Volumes 1 and 2.

Stanley Wolf Ph.D.