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Excerpt from: SILICON PROCESSING FOR THE VLSI ERA - Vol. 3
6.6 CMOS ISOLATION TECHNOLOGY pp. 373-378 by Stanley Wolf, Ph.D.
The material of this section has been reformatted to allow faster loading of the page. In CMOS ICs isolation must exist not only between like kinds of devices (e.g., between two n-channel transistors or two p-channel transistors within a given well or within the substrate region) but also between devices of opposite polarity (e.g., between p- and n-channel devices separated by at least one well). The isolation of like kind of devices involves the same techniques used to isolate the devices in either NMOS or PMOS circuits (i.e., a combination of a thick field oxide and channel-stop doping). However, the isolation of p-channel from n-channel devices involves additional considerations, insofar as two opposite-type FETs must be separated physically by at least one well. That is, in CMOS isolation two additional requirements that arise in neither PMOS or NMOS technology must be simultaneously satisfied: (1) any possible leakage currents that could flow between a p-channel device adjacent to an n-channel device must be suppressed; and (2) the susceptibility of CMOS to latchup must be minimized. In this section, we describe isolation techniques to suppress the leakage currents between n- and p-channel devices. Latchup suppression is described in Vol. 2, Chap. 6. Interest in isolating n- from p-channel devices is very keen because CMOS isolation structures generally consume much more chip area than the isolation structures needed between like types of devices. That is, earlier in this chapter we showed that isolation between like kinds of MOS devices can be realized with isolation spacings 1.0-µm. But in single-well CMOS technologies the minimum required isolation spacing is about three times the depth of the well. Thus, for a 4-µm-deep well, the minimum n+ to p+ spacing is ~12 µm. Even in twin-tub CMOS technologies with dual channel-stops, a minimum of 4-9 µm of lateral space is necessary for effective isolation. In advanced submicron CMOS technologies, it has been estimated that the minimum interwell (i.e., n+-to-p+) spacing is about three times the minimum intrawell (i.e., n+-to-n+ or p+-to-p+) spacing. The large area penalty of p-channel-to-n-channel device isolation is the most important reason why CMOS technologies using conventional isolation methods cannot achieve as high a packing density as NMOS. Furthermore, while new techniques such as epitaxy greatly reduce latchup susceptibility as CMOS is scaled down, they generally do not suppress leakage currents in the parasitic MOS structures.Thus, the layout spacing between n-channel & p-channel devices may be limited by isolation failure rather than by latchup. In this section we describe why greater isolation spacing is needed in CMOS than in NMOS or PMOS, and how the minimum spacing for a given CMOS technology is determined. We begin by considering CMOS isolation from a qualitative perspective. Next, we give a description of how CMOS isolation is quantitatively modeled. Then, test structures for empirically assessing the adequacy of isolation among opposite-type FETs in a CMOS technology are described. Procedures for establishing the design rules for minimum CMOS-isolation-spacing from the simulation results and measured data are then presented. Finally, technological approaches for fabricating isolation structures in CMOS are discussed. 6.6.1 Qualitative Description of Isolation in CMOS In CMOS structures, the isolation spacing between the n- and p-channel devices is defined as the sum of: (1) the distance between the edge of the n+ region of the n-channel device and the edge of the well; and (2) the distance between the edge of the p+ region of the p-channel device and the edge of the well (or, in other words, the n+ to p+ spacing, as shown in Fig. 6-43). As noted in the introduction, the minimum isolation spacing in CMOS is much larger than that required in NMOS or PMOS technologies. Here we explore the reasons why this is the case. |
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| Fig. 6-43 (a) Layout top view of the isolation region between n-type and p-type transistors in CMOS. (b) Cross sectional view of a CMOS inverter showing the channel stops that are designed to prevent the surface under the field oxide from inverting. (© 1986 IEEE). |
| An overall grasp of the issues of isolation in CMOS can be obtained by analyzing the various causes of leakage current in a CMOS inverter. The circuit schematic, layout, and a device cross-section of an n-well CMOS inverter is shown in Figs. 6-44a, b, and c, respectively. The layout actually shows two CMOS inverters connected in series, allowing the figure to be used to illustrate intra-well as well as inter-well isolation issues. In addition, the cross-section depicts an inverter with a different layout than the one shown in part (b) to enable us to show the source, drain, substrate and well contacts. Finally, note that n-well CMOS is chosen as the example CMOS architecture for this discussion, but the concepts are also equally valid for p-well and twin-well CMOS.
If a normally operating CMOS inverter is in one of its two logic states (i.e., it is not in transition between states), only a negligibly small leakage current IDD should exist between VDD and VSS. To ensure that the total IDD is within acceptably small limits, all of the sources of leakage between VDD and VSS need to be identified and characterized. Having such information in hand permits appropriate measures to be taken to assure that none of the leakage current components will exceed the maximum allowable IDD value. From this perspective, we can identify the sources of such leakage by dividing them up into two groups: (1) those which arise as a result of leakage phenomena within active devices or from isolation breakdown between like types of devices, and; (2) those which occur as a result of isolation failure in CMOS structures (e.g., loss of isolation between devices in the well and in the substrate). 6.6.1.1 Leakage Currents in CMOS Gates Due to Active Device Due to Active Device Phenomena and Intra-Well Isolation Loss The leakage-current phenomena associated with active devices and intra-well isolation structures have already been discussed in depth in Chaps. 4 and 5 and in earlier sections of Chap. 6. Therefore, they are considered here only in the context of their contribution to leakage in CMOS structures. Recall first that if a CMOS inverter is in one of its two logic states, one of the two complimentary MOS devices of the inverter will be OFF (see Fig. 6-44a). In the OFF state there are two components of leakage current that the device itself can contribute to IDD, namely the subthreshold drain current IDst (arising from either conventional subthreshold surface current or subsurface lateral-punchthrough current) and the reverse-biased drain-substrate junction leakage current. By proper circuit and device design these leakage components can be kept adequately small under normal operating conditions. In addition, leakage between the drain of one device and the source of neighboring devices within the same well (or substrate) constitutes another possible component of IDD (see Fig. 6-44b). Such leakage can be suppressed by the techniques used to isolate two n-channel (or p-channel) devices from one another, as described earlier in the chapter. In most cases, leakage current due to inadequate isolation among intra-well devices is due to surface inversion effects which permit excessive subthreshold drain current to flow in the intra-well parasitic field transistors, as described in Section 6.1. 6.6.1.2 Leakage Currents in CMOS Gates Due to Loss of Isolation Among Opposite-Type FETs. Basic isolation among opposite-type FETs in CMOS involves several considerations. The first and most obvious involves the suppression of leakage across the pn junction which isolates the well from the substrate. To keep the component of IDD due to this effect negligible, the well-substrate junction must always be kept under reverse bias. To ensure that this requirement is met (under normal operating conditions) the n-well (or n-substrate) is connected to the most positive circuit voltage (i.e., VDD), and the p-well (or p substrate) to the most negative circuit voltage (i.e., VSS), as shown in Fig. 6-44c for p-well CMOS. Other components of IDD in CMOS, however, can also arise from the loss of isolation involving leakage in the parasitic FETs created by the proximity of the active device source/drain regions and the well edges. There are two of these parasitic FETs formed at the edge of the n-well - one being a parasitic NMOSFET and the other a parasitic PMOSFET (as shown in Fig. 6-45). Notice that the n+ and n-well (and the p+ and p-substrate), form the source and drain for such parasitic NMOSFETs (and PMOSFETs), respectively. The p-substrate and n-well are the channels of these parasitic NMOS and PMOS FETs respectively, and the field oxide and poly (or Al) runners over the field oxide form the gate oxide and gates of these parasitic structures. However, it is important to note that unlike in active MOSFETs, the source and drain in these parasitic FETs are not symmetrical. That is, the substrate and well are deep junctions and the n+ and p+ regions are shallow junctions. Because a deeper drain junction and a highly conductive source always produce more subthreshold current (thereby representing a worst case condition for isolation), the n-well and p-substrate are designated as the drains when characterizing the behavior in these parasitic asymmetric FET structures. |
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| Fig. 6-44 (a) Circuit schematic of two CMOS inverters connected in series. (b) Layout of two n-well CMOS inverters connected in series. (c) Cross-section of a CMOS inverter, showing also the well & substrate contacts. |
| Here we identify the phenomena in these parasitic FETs that can give rise to leakage current components in CMOS (again using n-well CMOS as the example CMOS architecture). Later we will describe techniques for mitigating these leakage currents. First, we point out that while the n-well (or n-substrate) is connected to VDD, the n+ source or drain regions can be biased at VSS. (As an example, the n+ source of the NMOS device in the CMOS inverter is connected to VSS.)
Thus, if a leakage path exists between the n-well and the n+ source, the potential difference between the n-substrate and the n+ regions can cause a component of IDD to flow between VDD and VSS. The same problem arises between the p+ source regions in the well and the p-substrate. It is also important to note that each of the parasitic FETs in which such leakage paths can arise act independently. Thus, when a CMOS technology is being developed, all of the parasitic FETs must be must be designed correctly to prevent any one of them from drawing a significant IDD. |
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| Fig. 6-45 Parasitic MOS transistors formed at the well-edge in n-well CMOS. (© IEEE 1987). |
| The leakage paths which can be established in the parasitic FETs of an n-well CMOS structure are the following:
1. Inversion of the channel region of the n+-to-n-well parasitic FET. |
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